14 封裝術語
來源：Hitachi Semiconductor Package Data Book. ADE–410–001H, 9th Edition. March (2001)
為了更好的理解相關的封裝術語，下面進行了更為詳細的羅列：
來自：smta.org：電子封裝術語

ASIC Application Specific Integrated Circuit
專用集成電路
BGA Ball Grid Array. A component whose terminations are on the bottom of the package, and are in the shape of solder balls and in a grid array pattern. This generally covers components that have them in a full array or in a partial array with “missing” balls in the center.
球形觸點陳列，表面貼裝型封裝之一。在印刷基板的背面按陳列方式制作出球形凸點用以
代替引腳，在印刷基板的正面裝配LSI 芯片，然后用模壓樹脂或灌封方法進行密封。也稱為凸點陳列載體(PAC)。引腳可超過200，是多引腳LSI 用的一種封裝。
CBGA/CCGA Ceramic Ball Grid Array/Ceramic Column Grid Array. A grid array packaged component that has ceramic as the substrate of the package, and may have either solder balls or solder columns for connections.
CMOS Complementary Metal Oxide Semiconductor
互補型金屬氧化物半導體
COB Chip-on-Board. A situation where the silicon IC chip is mounted directly to the electronic assembly substrate or PWB without an intermediate packaging step. Connections between the chip and the board are generally made with bond wired (also sometime called chip and wire), but the terminology is occasionally used for any chip connection technique such as flip chip (solderable bumps or tape automated bonding.
板上芯片封裝，是裸芯片貼裝技術之一，半導體芯片交接貼裝在印刷線路板上，芯片與基
板的電氣連接用引線縫合方法實現，芯片與基板的電氣連接用引線縫合方法實現，并用樹脂覆蓋以確?？煽啃?。雖然COB 是最簡單的裸芯片貼裝技術，但它的封裝密度遠不如TAB 和倒片焊技術。
CSP Chip Scale Package. Active, multi-I/O package that is no larger than 125% of the size of the silicon IC.
芯片級封裝
DIL Dual In-Line. Component shape with two parallel rows of connection leads.
DIP 的別稱(見DIP)。歐洲半導體廠家多用此名稱。
DIP Dual In-Line Package. A popular through hole package with leads in rows on opposite sides of the package.
雙列直插式封裝。插裝型封裝之一，引腳從封裝兩側引出，封裝材料有塑料和陶瓷兩種。DIP 是最普及的插裝型封裝，應用范圍包括標準邏輯IC，存貯器LSI，微機電路等。引腳中心距2.54mm，引腳數從6 到64。封裝寬度通常為15.2mm。有的把寬度為7.52mm和10.16mm 的封裝分別稱為skinny DIP 和slim DIP(窄體型DIP)。但多數情況下并不加區分，只簡單地統稱為DIP。
FCA Flip Chip Attach. The technique of attachment of an IC chip to a substrate using solderable bumps between the silicon chip and substrate.

FPT Fine Pitch Technology. The portion of surface mount technology that included components that typically have lead pitch, or center-to-center spacing, between 0.4mm and 0.8mm.
微間距技術
FP Flat Pack. A low profile IC package, which typically has gull wing type of leads on two or four sides.
扁平封裝
FR-4 The most commonly used epoxy-fiberglass material standard for printed circuit boards. The “FR” refers to flame retardant.
由專用電子布浸以環氧酚醛樹脂等材料經高溫高壓熱壓而成的板狀層壓制品。
IC Integrated Circuit. A small, complete circuit made by vacuum deposition and other techniques, usually on a silicon chip, and mounted in a package.
集成電路
JEDEC Joint Electronic Devices Engineering Council, a part of the Electronic Industries Association (EIA) that publishes specifications and standards for electronic components.
電子設備工業聯合會
LCCC Leadless Ceramic Chip Carrier (or CLCC for Ceramic Leadless Chip Carrier). A hermetically sealed ceramic package that has pads (castellations) around its sides for solder connection in a surface mounting application.
無引線陶瓷芯片載體
LDCC Leaded Ceramic Chip Carrier. A hermetically sealed ceramic package that has leads around its sided for solder connection in a surface mounting application. Typically, thee packages have over 28 leads.
帶引腳的陶瓷芯片載體
MCM Multichip Module. A circuit comprised of two or more silicon devices bonded directly to a substrate by wire bond, TAB, of flip chip.
多芯片組件
MELF Metal Electrode Face Bonding. A cylindrical leadless component with a round body and metals terminals on the ends.
金屬電極表面接合
PBGA Plastic Ball Grid Array. A ball grid array component whose package substrate is made of plastic, most likely an FR-4 equivalent of epoxy-fiberglass, polyimidearramid, or similar resin-fiber combinations.
塑封球柵陣列型封裝
PCB Printed Circuit Board. A part manufactured from a rigid base material upon which a completely processed printed circuit has been formed.
印制電路板
PGA Pad Grid Array. Similar to a pin grid array. An IC package that has solderable connections in a grid layout on the bottom of the package, and is soldered to the surface of the substrate (PWB) with butt solder joints.
陳列引腳封裝。插裝型封裝之一，其底面的垂直引腳呈陳列狀排列。封裝基材基本上都采用多層陶瓷基板。在未專門表示出材料名稱的情況下，多數為陶瓷PGA，用于高速大規模邏輯LSI 電路。成本較高。引腳中心距通常為2.54mm，引腳數從64 到447 左右。為降低成本，封裝基材可用玻璃環氧樹脂印刷基板代替。也有64～256 引腳的塑料PGA。另外，還有一種引腳中心距為1.27mm 的短引腳表面貼裝型PGA(碰焊PGA)。
PLCC Plastic Leaded Chip Carrier. A plastic IC package for surface mounting applications that has leads, generally “J” leads, on all fours sides (sometimes given as PCC or PLDCC).
帶引線的塑料芯片載體。表面貼裝型封裝之一。引腳從封裝的四個側面引出，呈丁字形，是塑料制品。美國德克薩斯儀器公司首先在64k 位DRAM 和256kDRAM 中采用，現在已經普及用于邏輯LSI、DLD(或程邏輯器件)等電路。引腳中心距1.27mm，引腳數從18 到84。J 形引腳不易變形，比QFP 容易操作，但焊接后的外觀檢查較為困難。
PQFP Plastic Quad Flat Pack. An FP with leads on fours sides. Generally refers to a plastic quad flat package that is built to JEDC standards.
塑料四方扁平封裝
QFP Quad Flat Pack. A FP with leads on four sides. Generally refers to a plastic quad flat package that is built to EIJ standards.
四側引腳扁平封裝。表面貼裝型封裝之一，引腳從四個側面引出呈海鷗翼(L)型?；挠刑沾?、金屬和塑料三種。從數量上看，塑料封裝占絕大部分。當沒有特別表示出材料時，多數情況為塑料QFP。
QSOP Quarter-Size Small Outline Package. An SO style IC package that has leads on a 25 mil pitch. The name derives from the fact that the package is approximately ½ the length and ½ the width of a standard SOIC, and thus a package of the same pin count occupies approximately ¼ the area on a PWB.
四分之一縮比小外廓封裝
SIP Single-In-Line Package. An IC package or multi-component sub-assembly that has connections or leads in a single row on one side.
單列直插式封裝
SO Small Outline. A package resembling a flat pack with leads on only two sides.

SOIC Small Outline Integrated Circuit. A plastic IC package for surface mounting applications that has leads on two opposite sides.
小塊集成電路
SOJ A plastic IC package with “J” leads on two sides. It resembles a plastic DIP or an SOIC except for lead spacing and forming.
J 形引腳小外型封裝。表面貼裝型封裝之一。引腳從封裝兩側引出向下呈J 字形，故此得名。通常為塑料制品，多數用于DRAM 和SRAM 等存儲器LSI 電路，但絕大部分是DRAM。用SOJ封裝的DRAM 器件很多都裝配在SIMM 上。引腳中心距1.27mm，引腳數從20 至40(見SIMM)。
SOL/SOW Small Outline-Large/Small Outline Wide. SO generally refers to a package that  is approximately 150 mils wide, while SOL/SOW refers to packages that are approximately 300 mils wide.

SOP VSOP/SSOP. Another designation for the small outline ICP packages, i.e. Small Outline Package (Very Small Outline Package, Shrink Small Outline Package)
SOP 除了用于存儲器LSI 外，也廣泛用于規模不太大的ASSP 等電路。在輸入輸出端子不超過10～40 的領域，SOP 是普及最廣的表面貼裝封裝。引腳中心距1.27mm，引腳數從8～44。另外，引腳中心距小于1.27mm 的SOP 也稱為SSOP；裝配高度不到1.27mm 的SOP 也稱為TSOP(見SSOP、TSOP)。還有一種帶有散熱片的SOP。
SOT Small Outline Transistor. A plastic leaded package for diodes and transistors used in surface mounting applications.
小外形晶體管
SPC Statistical Process Control. The use of statistical techniques to analyze a process or its output to determine any variation from a benchmark and to take appropriate action to restore statistical control, if required.
統計過程控制
SSOIC Shrink Small Outline IC. An SO style IC package that has leads on a 25 mil pitch.
超小輪廓封裝
TBGA Tape Ball Grid Array. A ball grid array component package that uses TAB techniques to make the connections between the IC chip and the solder balls. This results in a solder ball grid array that is only around the periphery, and leaves compliant connections between the IC and the solder balls for better TCE reliability.
載帶球柵陣列
VFP Very Fine Pitch. The center-to-center lead distance of surface mount packages that are between 0.012 inch and 0.020 inch.

VSOIC Very Small Outline IC. An SO style IC package that has leads with a pitch of 30 mils or less.

Sources Used:
“Understanding and Using Surface Mount and Fine Pitch Technology”, Charles Hutchins, 1995.
“Surface Mount Technology: Principles and Practice”, Ray Prasad, 1997.
“Surface Mount Technology Terms and Concepts”, Phil Zarrow and Debra Kopp, ITM, 1997.

 Flotherm資料下載: 使用Flotherm進行電子散熱仿真過程中涉及的物理學原理.pdf

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